1. Field of the Invention
The present invention relates to a method for a burn-in test.
2. Description of the Related Art
Various mounting techniques are developed to attain a high density mounting of a semiconductor device. For example, TAB (Tape Automated Bonding) or COF (Chip on Film) is often employed to mount the semiconductor device on a carrier tape for a liquid crystal driver IC. Also, CSP (Chip Size Packaging) or MCP (Multi-Chip Package) is often employed for a portable apparatus IC.
One of items to be considered in employing the foregoing mounting techniques is an execution method for a burn-in. To secure KGD (Known Good Die) having a high reliability, it is essentially necessary to execute the burn-in. However, when the mounting technique such as the TAB, COF, CSP or MCP is employed, the burn-in using a burn-in board can not be executed unlike in the case of a typical semiconductor device. For the mounting technique such as the TAB, COF, CSP or MCP, it is necessary to execute the burn-in without using the burn-in board.
To execute the burn-in without using the burn-in board, the burn-in technique using probes is considered. One of the examples is a wafer level burn-in (WLBI) technique in which the burn-in is performed on a semiconductor device in its original wafer. Japanese Laid Open Patent Application JP 2003-297887A discloses the WLBI technique. In the wafer level burn-in, the probes are brought into contact with the semiconductor device on the original wafer, and stress is applied through the probes to the semiconductor device.
One problem of the burn-in test technique that uses the probes lies in a long testing time. To make the testing time shorter, it is preferable to simultaneously apply the burn-in to many semiconductor devices by using a single probe card. For example, in the wafer level burn-in technique, it is ideal to simultaneously apply the burn-in to all the semiconductor devices formed in one wafer by using the single probe card. However, the simultaneous application of the burn-in to the many semiconductor devices makes the securing of the reliability of the electrical connection between the probe and the semiconductor device difficult. Actually, the plurality of the tests must be inevitably executed for testing the semiconductor devices. However, if the plurality of the tests is executed for testing the semiconductor devices, this correspondingly leads to the increase in the testing time. The increase in the testing time is not preferable because it causes the increase in a testing cost.
In view of the foregoing background, it is desired to provide a technique for reducing the testing time of the burn-in test using the probe.